// Generator : SpinalHDL v1.10.2a    git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935
// Component : MyTopLevel
// Git hash  : 8456715b1c403daf6e88b4348fb6208a3582b074

`timescale 1ns/1ps

module test_axi (
  input  wire          axi_awvalid,
  output wire          axi_awready,
  input  wire [19:0]   axi_awaddr,
  input  wire [1:0]    axi_awid,
  input  wire [3:0]    axi_awregion,
  input  wire [7:0]    axi_awlen,
  input  wire [2:0]    axi_awsize,
  input  wire [1:0]    axi_awburst,
  input  wire [0:0]    axi_awlock,
  input  wire [3:0]    axi_awcache,
  input  wire [3:0]    axi_awqos,
  input  wire [2:0]    axi_awprot,
  input  wire          axi_wvalid,
  output wire          axi_wready,
  input  wire [31:0]   axi_wdata,
  input  wire [3:0]    axi_wstrb,
  input  wire          axi_wlast,
  output wire          axi_bvalid,
  input  wire          axi_bready,
  output wire [1:0]    axi_bid,
  output wire [1:0]    axi_bresp,
  input  wire          axi_arvalid,
  output wire          axi_arready,
  input  wire [19:0]   axi_araddr,
  input  wire [1:0]    axi_arid,
  input  wire [3:0]    axi_arregion,
  input  wire [7:0]    axi_arlen,
  input  wire [2:0]    axi_arsize,
  input  wire [1:0]    axi_arburst,
  input  wire [0:0]    axi_arlock,
  input  wire [3:0]    axi_arcache,
  input  wire [3:0]    axi_arqos,
  input  wire [2:0]    axi_arprot,
  output wire          axi_rvalid,
  input  wire          axi_rready,
  output wire [31:0]   axi_rdata,
  output wire [1:0]    axi_rid,
  output wire [1:0]    axi_rresp,
  output wire          axi_rlast,
  output wire [19:0]   apbOut_PADDR,
  output wire [0:0]    apbOut_PSEL,
  output wire          apbOut_PENABLE,
 // input  wire          apbOut_PREADY,
  output wire          apbOut_PWRITE,
  output wire [31:0]   apbOut_PWDATA,
 // input  wire [31:0]   apbOut_PRDATA,
 // input  wire          apbOut_PSLVERROR,
  input  wire          clk,
  input  wire          rst
);

  wire                bridge_io_axi_arw_payload_write;
  wire                bridge_io_axi_arw_ready;
  wire                bridge_io_axi_w_ready;
  wire                bridge_io_axi_b_valid;
  wire       [1:0]    bridge_io_axi_b_payload_id;
  wire       [1:0]    bridge_io_axi_b_payload_resp;
  wire                bridge_io_axi_r_valid;
  wire       [31:0]   bridge_io_axi_r_payload_data;
  wire       [1:0]    bridge_io_axi_r_payload_id;
  wire       [1:0]    bridge_io_axi_r_payload_resp;
  wire                bridge_io_axi_r_payload_last;
  wire       [19:0]   bridge_io_apb_PADDR;
  wire       [0:0]    bridge_io_apb_PSEL;
  wire                bridge_io_apb_PENABLE;
  wire                bridge_io_apb_PWRITE;
  wire       [31:0]   bridge_io_apb_PWDATA;
  wire                streamArbiter_1_io_inputs_0_ready;
  wire                streamArbiter_1_io_inputs_1_ready;
  wire                streamArbiter_1_io_output_valid;
  wire       [19:0]   streamArbiter_1_io_output_payload_addr;
  wire       [1:0]    streamArbiter_1_io_output_payload_id;
  wire       [3:0]    streamArbiter_1_io_output_payload_region;
  wire       [7:0]    streamArbiter_1_io_output_payload_len;
  wire       [2:0]    streamArbiter_1_io_output_payload_size;
  wire       [1:0]    streamArbiter_1_io_output_payload_burst;
  wire       [0:0]    streamArbiter_1_io_output_payload_lock;
  wire       [3:0]    streamArbiter_1_io_output_payload_cache;
  wire       [3:0]    streamArbiter_1_io_output_payload_qos;
  wire       [2:0]    streamArbiter_1_io_output_payload_prot;
  wire       [0:0]    streamArbiter_1_io_chosen;
  wire       [1:0]    streamArbiter_1_io_chosenOH;

  Axi4SharedToApb3Bridge bridge (
    .io_axi_arw_valid         (streamArbiter_1_io_output_valid             ), //i
    .io_axi_arw_ready         (bridge_io_axi_arw_ready                     ), //o
    .io_axi_arw_payload_addr  (streamArbiter_1_io_output_payload_addr[19:0]), //i
    .io_axi_arw_payload_id    (streamArbiter_1_io_output_payload_id[1:0]   ), //i
    .io_axi_arw_payload_len   (streamArbiter_1_io_output_payload_len[7:0]  ), //i
    .io_axi_arw_payload_size  (streamArbiter_1_io_output_payload_size[2:0] ), //i
    .io_axi_arw_payload_burst (streamArbiter_1_io_output_payload_burst[1:0]), //i
    .io_axi_arw_payload_write (bridge_io_axi_arw_payload_write             ), //i
    .io_axi_w_valid           (axi_wvalid                                ), //i
    .io_axi_w_ready           (bridge_io_axi_w_ready                       ), //o
    .io_axi_w_payload_data    (axi_wdata[31:0]                           ), //i
    .io_axi_w_payload_strb    (axi_wstrb[3:0]                            ), //i
    .io_axi_w_payload_last    (axi_wlast                                 ), //i
    .io_axi_b_valid           (bridge_io_axi_b_valid                       ), //o
    .io_axi_b_ready           (axi_bready                                ), //i
    .io_axi_b_payload_id      (bridge_io_axi_b_payload_id[1:0]             ), //o
    .io_axi_b_payload_resp    (bridge_io_axi_b_payload_resp[1:0]           ), //o
    .io_axi_r_valid           (bridge_io_axi_r_valid                       ), //o
    .io_axi_r_ready           (axi_rready                                ), //i
    .io_axi_r_payload_data    (bridge_io_axi_r_payload_data[31:0]          ), //o
    .io_axi_r_payload_id      (bridge_io_axi_r_payload_id[1:0]             ), //o
    .io_axi_r_payload_resp    (bridge_io_axi_r_payload_resp[1:0]           ), //o
    .io_axi_r_payload_last    (bridge_io_axi_r_payload_last                ), //o
    .io_apb_PADDR             (bridge_io_apb_PADDR[19:0]                   ), //o
    .io_apb_PSEL              (bridge_io_apb_PSEL                          ), //o
    .io_apb_PENABLE           (bridge_io_apb_PENABLE                       ), //o
    //.io_apb_PREADY            (apbOut_PREADY                               ), //i
    .io_apb_PREADY            (1'b1                               ), //i
    .io_apb_PWRITE            (bridge_io_apb_PWRITE                        ), //o
    .io_apb_PWDATA            (bridge_io_apb_PWDATA[31:0]                  ), //o
    //.io_apb_PRDATA            (apbOut_PRDATA[31:0]                         ), //i
    .io_apb_PRDATA            (32'b0                         ), //i
    //.io_apb_PSLVERROR         (apbOut_PSLVERROR                            ), //i
    .io_apb_PSLVERROR         (1'b0                            ), //i
    .clk                      (clk                                         ), //i
    .rst                    (rst                                       )  //i
  );
  StreamArbiter streamArbiter_1 (
    .io_inputs_0_valid          (axi_arvalid                                ), //i
    .io_inputs_0_ready          (streamArbiter_1_io_inputs_0_ready            ), //o
    .io_inputs_0_payload_addr   (axi_araddr[19:0]                           ), //i
    .io_inputs_0_payload_id     (axi_arid[1:0]                              ), //i
    .io_inputs_0_payload_region (axi_arregion[3:0]                          ), //i
    .io_inputs_0_payload_len    (axi_arlen[7:0]                             ), //i
    .io_inputs_0_payload_size   (axi_arsize[2:0]                            ), //i
    .io_inputs_0_payload_burst  (axi_arburst[1:0]                           ), //i
    .io_inputs_0_payload_lock   (axi_arlock                                 ), //i
    .io_inputs_0_payload_cache  (axi_arcache[3:0]                           ), //i
    .io_inputs_0_payload_qos    (axi_arqos[3:0]                             ), //i
    .io_inputs_0_payload_prot   (axi_arprot[2:0]                            ), //i
    .io_inputs_1_valid          (axi_awvalid                                ), //i
    .io_inputs_1_ready          (streamArbiter_1_io_inputs_1_ready            ), //o
    .io_inputs_1_payload_addr   (axi_awaddr[19:0]                           ), //i
    .io_inputs_1_payload_id     (axi_awid[1:0]                              ), //i
    .io_inputs_1_payload_region (axi_awregion[3:0]                          ), //i
    .io_inputs_1_payload_len    (axi_awlen[7:0]                             ), //i
    .io_inputs_1_payload_size   (axi_awsize[2:0]                            ), //i
    .io_inputs_1_payload_burst  (axi_awburst[1:0]                           ), //i
    .io_inputs_1_payload_lock   (axi_awlock                                 ), //i
    .io_inputs_1_payload_cache  (axi_awcache[3:0]                           ), //i
    .io_inputs_1_payload_qos    (axi_awqos[3:0]                             ), //i
    .io_inputs_1_payload_prot   (axi_awprot[2:0]                            ), //i
    .io_output_valid            (streamArbiter_1_io_output_valid              ), //o
    .io_output_ready            (bridge_io_axi_arw_ready                      ), //i
    .io_output_payload_addr     (streamArbiter_1_io_output_payload_addr[19:0] ), //o
    .io_output_payload_id       (streamArbiter_1_io_output_payload_id[1:0]    ), //o
    .io_output_payload_region   (streamArbiter_1_io_output_payload_region[3:0]), //o
    .io_output_payload_len      (streamArbiter_1_io_output_payload_len[7:0]   ), //o
    .io_output_payload_size     (streamArbiter_1_io_output_payload_size[2:0]  ), //o
    .io_output_payload_burst    (streamArbiter_1_io_output_payload_burst[1:0] ), //o
    .io_output_payload_lock     (streamArbiter_1_io_output_payload_lock       ), //o
    .io_output_payload_cache    (streamArbiter_1_io_output_payload_cache[3:0] ), //o
    .io_output_payload_qos      (streamArbiter_1_io_output_payload_qos[3:0]   ), //o
    .io_output_payload_prot     (streamArbiter_1_io_output_payload_prot[2:0]  ), //o
    .io_chosen                  (streamArbiter_1_io_chosen                    ), //o
    .io_chosenOH                (streamArbiter_1_io_chosenOH[1:0]             ), //o
    .clk                        (clk                                          ), //i
    .rst                      (rst                                        )  //i
  );
  assign axi_arready = streamArbiter_1_io_inputs_0_ready;
  assign axi_awready = streamArbiter_1_io_inputs_1_ready;
  assign axi_wready = bridge_io_axi_w_ready;
  assign axi_bvalid = bridge_io_axi_b_valid;
  assign axi_bid = bridge_io_axi_b_payload_id;
  assign axi_bresp = bridge_io_axi_b_payload_resp;
  assign axi_rvalid = bridge_io_axi_r_valid;
  assign axi_rdata = bridge_io_axi_r_payload_data;
  assign axi_rid = bridge_io_axi_r_payload_id;
  assign axi_rresp = bridge_io_axi_r_payload_resp;
  assign axi_rlast = bridge_io_axi_r_payload_last;
  assign bridge_io_axi_arw_payload_write = streamArbiter_1_io_chosenOH[1];
  assign apbOut_PADDR = bridge_io_apb_PADDR;
  assign apbOut_PSEL = bridge_io_apb_PSEL;
  assign apbOut_PENABLE = bridge_io_apb_PENABLE;
  assign apbOut_PWRITE = bridge_io_apb_PWRITE;
  assign apbOut_PWDATA = bridge_io_apb_PWDATA;

endmodule

module StreamArbiter (
  input  wire          io_inputs_0_valid,
  output wire          io_inputs_0_ready,
  input  wire [19:0]   io_inputs_0_payload_addr,
  input  wire [1:0]    io_inputs_0_payload_id,
  input  wire [3:0]    io_inputs_0_payload_region,
  input  wire [7:0]    io_inputs_0_payload_len,
  input  wire [2:0]    io_inputs_0_payload_size,
  input  wire [1:0]    io_inputs_0_payload_burst,
  input  wire [0:0]    io_inputs_0_payload_lock,
  input  wire [3:0]    io_inputs_0_payload_cache,
  input  wire [3:0]    io_inputs_0_payload_qos,
  input  wire [2:0]    io_inputs_0_payload_prot,
  input  wire          io_inputs_1_valid,
  output wire          io_inputs_1_ready,
  input  wire [19:0]   io_inputs_1_payload_addr,
  input  wire [1:0]    io_inputs_1_payload_id,
  input  wire [3:0]    io_inputs_1_payload_region,
  input  wire [7:0]    io_inputs_1_payload_len,
  input  wire [2:0]    io_inputs_1_payload_size,
  input  wire [1:0]    io_inputs_1_payload_burst,
  input  wire [0:0]    io_inputs_1_payload_lock,
  input  wire [3:0]    io_inputs_1_payload_cache,
  input  wire [3:0]    io_inputs_1_payload_qos,
  input  wire [2:0]    io_inputs_1_payload_prot,
  output wire          io_output_valid,
  input  wire          io_output_ready,
  output wire [19:0]   io_output_payload_addr,
  output wire [1:0]    io_output_payload_id,
  output wire [3:0]    io_output_payload_region,
  output wire [7:0]    io_output_payload_len,
  output wire [2:0]    io_output_payload_size,
  output wire [1:0]    io_output_payload_burst,
  output wire [0:0]    io_output_payload_lock,
  output wire [3:0]    io_output_payload_cache,
  output wire [3:0]    io_output_payload_qos,
  output wire [2:0]    io_output_payload_prot,
  output wire [0:0]    io_chosen,
  output wire [1:0]    io_chosenOH,
  input  wire          clk,
  input  wire          rst
);

  wire       [3:0]    _zz__zz_maskProposal_0_2;
  wire       [3:0]    _zz__zz_maskProposal_0_2_1;
  wire       [1:0]    _zz__zz_maskProposal_0_2_2;
  reg                 locked;
  wire                maskProposal_0;
  wire                maskProposal_1;
  reg                 maskLocked_0;
  reg                 maskLocked_1;
  wire                maskRouted_0;
  wire                maskRouted_1;
  wire       [1:0]    _zz_maskProposal_0;
  wire       [3:0]    _zz_maskProposal_0_1;
  wire       [3:0]    _zz_maskProposal_0_2;
  wire       [1:0]    _zz_maskProposal_0_3;
  wire                io_output_fire;
  wire                _zz_io_chosen;

  assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1);
  assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1};
  assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2};
  assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
  assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1);
  assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid};
  assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0};
  assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2));
  assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]);
  assign maskProposal_0 = _zz_maskProposal_0_3[0];
  assign maskProposal_1 = _zz_maskProposal_0_3[1];
  assign io_output_fire = (io_output_valid && io_output_ready);
  assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1));
  assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr);
  assign io_output_payload_id = (maskRouted_0 ? io_inputs_0_payload_id : io_inputs_1_payload_id);
  assign io_output_payload_region = (maskRouted_0 ? io_inputs_0_payload_region : io_inputs_1_payload_region);
  assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len);
  assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size);
  assign io_output_payload_burst = (maskRouted_0 ? io_inputs_0_payload_burst : io_inputs_1_payload_burst);
  assign io_output_payload_lock = (maskRouted_0 ? io_inputs_0_payload_lock : io_inputs_1_payload_lock);
  assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache);
  assign io_output_payload_qos = (maskRouted_0 ? io_inputs_0_payload_qos : io_inputs_1_payload_qos);
  assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot);
  assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
  assign io_inputs_1_ready = (maskRouted_1 && io_output_ready);
  assign io_chosenOH = {maskRouted_1,maskRouted_0};
  assign _zz_io_chosen = io_chosenOH[1];
  assign io_chosen = _zz_io_chosen;
  always @(posedge clk or posedge rst) begin
    if(rst) begin
      locked <= 1'b0;
      maskLocked_0 <= 1'b0;
      maskLocked_1 <= 1'b1;
    end else begin
      if(io_output_valid) begin
        maskLocked_0 <= maskRouted_0;
        maskLocked_1 <= maskRouted_1;
      end
      if(io_output_valid) begin
        locked <= 1'b1;
      end
      if(io_output_fire) begin
        locked <= 1'b0;
      end
    end
  end


endmodule

module Axi4SharedToApb3Bridge (
  input  wire          io_axi_arw_valid,
  output reg           io_axi_arw_ready,
  input  wire [19:0]   io_axi_arw_payload_addr,
  input  wire [1:0]    io_axi_arw_payload_id,
  input  wire [7:0]    io_axi_arw_payload_len,
  input  wire [2:0]    io_axi_arw_payload_size,
  input  wire [1:0]    io_axi_arw_payload_burst,
  input  wire          io_axi_arw_payload_write,
  input  wire          io_axi_w_valid,
  output reg           io_axi_w_ready,
  input  wire [31:0]   io_axi_w_payload_data,
  input  wire [3:0]    io_axi_w_payload_strb,
  input  wire          io_axi_w_payload_last,
  output reg           io_axi_b_valid,
  input  wire          io_axi_b_ready,
  output wire [1:0]    io_axi_b_payload_id,
  output wire [1:0]    io_axi_b_payload_resp,
  output reg           io_axi_r_valid,
  input  wire          io_axi_r_ready,
  output wire [31:0]   io_axi_r_payload_data,
  output wire [1:0]    io_axi_r_payload_id,
  output wire [1:0]    io_axi_r_payload_resp,
  output wire          io_axi_r_payload_last,
  output wire [19:0]   io_apb_PADDR,
  output reg  [0:0]    io_apb_PSEL,
  output reg           io_apb_PENABLE,
  input  wire          io_apb_PREADY,
  output wire          io_apb_PWRITE,
  output wire [31:0]   io_apb_PWDATA,
  input  wire [31:0]   io_apb_PRDATA,
  input  wire          io_apb_PSLVERROR,
  input  wire          clk,
  input  wire          rst
);
  localparam Axi4ToApb3BridgePhase_SETUP = 2'd0;
  localparam Axi4ToApb3BridgePhase_ACCESS_1 = 2'd1;
  localparam Axi4ToApb3BridgePhase_RESPONSE = 2'd2;

  reg        [1:0]    phase;
  reg                 write;
  reg        [31:0]   readedData;
  reg        [1:0]    id;
  wire                when_Axi4SharedToApb3Bridge_l91;
  wire                when_Axi4SharedToApb3Bridge_l97;
  `ifndef SYNTHESIS
  reg [63:0] phase_string;
  `endif


  `ifndef SYNTHESIS
  always @(*) begin
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : phase_string = "SETUP   ";
      Axi4ToApb3BridgePhase_ACCESS_1 : phase_string = "ACCESS_1";
      Axi4ToApb3BridgePhase_RESPONSE : phase_string = "RESPONSE";
      default : phase_string = "????????";
    endcase
  end
  `endif

  always @(*) begin
    io_axi_arw_ready = 1'b0;
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
        if(when_Axi4SharedToApb3Bridge_l91) begin
          if(when_Axi4SharedToApb3Bridge_l97) begin
            io_axi_arw_ready = 1'b1;
          end
        end
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
        if(io_apb_PREADY) begin
          io_axi_arw_ready = 1'b1;
        end
      end
      default : begin
      end
    endcase
  end

  always @(*) begin
    io_axi_w_ready = 1'b0;
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
        if(when_Axi4SharedToApb3Bridge_l91) begin
          if(when_Axi4SharedToApb3Bridge_l97) begin
            io_axi_w_ready = 1'b1;
          end
        end
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
        if(io_apb_PREADY) begin
          io_axi_w_ready = write;
        end
      end
      default : begin
      end
    endcase
  end

  always @(*) begin
    io_axi_b_valid = 1'b0;
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
      end
      default : begin
        if(write) begin
          io_axi_b_valid = 1'b1;
        end
      end
    endcase
  end

  always @(*) begin
    io_axi_r_valid = 1'b0;
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
      end
      default : begin
        if(!write) begin
          io_axi_r_valid = 1'b1;
        end
      end
    endcase
  end

  always @(*) begin
    io_apb_PSEL[0] = 1'b0;
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
        if(when_Axi4SharedToApb3Bridge_l91) begin
          io_apb_PSEL[0] = 1'b1;
          if(when_Axi4SharedToApb3Bridge_l97) begin
            io_apb_PSEL[0] = 1'b0;
          end
        end
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
        io_apb_PSEL[0] = 1'b1;
      end
      default : begin
      end
    endcase
  end

  always @(*) begin
    io_apb_PENABLE = 1'b0;
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
        io_apb_PENABLE = 1'b1;
      end
      default : begin
      end
    endcase
  end

  assign when_Axi4SharedToApb3Bridge_l91 = (io_axi_arw_valid && ((! io_axi_arw_payload_write) || io_axi_w_valid));
  assign when_Axi4SharedToApb3Bridge_l97 = (io_axi_arw_payload_write && (io_axi_w_payload_strb == 4'b0000));
  assign io_apb_PADDR = io_axi_arw_payload_addr;
  assign io_apb_PWDATA = io_axi_w_payload_data;
  assign io_apb_PWRITE = io_axi_arw_payload_write;
  assign io_axi_r_payload_resp = {io_apb_PSLVERROR,1'b0};
  assign io_axi_b_payload_resp = {io_apb_PSLVERROR,1'b0};
  assign io_axi_r_payload_id = id;
  assign io_axi_b_payload_id = id;
  assign io_axi_r_payload_data = readedData;
  assign io_axi_r_payload_last = 1'b1;
  always @(posedge clk or posedge rst) begin
    if(rst) begin
      phase <= Axi4ToApb3BridgePhase_SETUP;
    end else begin
      case(phase)
        Axi4ToApb3BridgePhase_SETUP : begin
          if(when_Axi4SharedToApb3Bridge_l91) begin
            phase <= Axi4ToApb3BridgePhase_ACCESS_1;
            if(when_Axi4SharedToApb3Bridge_l97) begin
              phase <= Axi4ToApb3BridgePhase_RESPONSE;
            end
          end
        end
        Axi4ToApb3BridgePhase_ACCESS_1 : begin
          if(io_apb_PREADY) begin
            phase <= Axi4ToApb3BridgePhase_RESPONSE;
          end
        end
        default : begin
          if(write) begin
            if(io_axi_b_ready) begin
              phase <= Axi4ToApb3BridgePhase_SETUP;
            end
          end else begin
            if(io_axi_r_ready) begin
              phase <= Axi4ToApb3BridgePhase_SETUP;
            end
          end
        end
      endcase
    end
  end

  always @(posedge clk) begin
    case(phase)
      Axi4ToApb3BridgePhase_SETUP : begin
        write <= io_axi_arw_payload_write;
        id <= io_axi_arw_payload_id;
      end
      Axi4ToApb3BridgePhase_ACCESS_1 : begin
        if(io_apb_PREADY) begin
          readedData <= io_apb_PRDATA;
        end
      end
      default : begin
      end
    endcase
  end


endmodule
